The Heat Moves Inside

The next bottleneck in advanced chips is not lithography, and it is not EUV. It is plumbing. At SEMICON Taiwan’s Heterogeneous Integration Summit on September 1, TSMC’s advanced-packaging leadership laid out the arithmetic: AI package power is on track to rise from roughly 600 watts per CoWoS package today to about 4,100 watts within five years — nearly a sevenfold increase, delivered into the same footprint. The company’s answer is a roadmap item that would have sounded absurd at a chip conference a decade ago: microchannel cooling, etched into the silicon itself.

The numbers behind the headline are just as loud. TSMC says demand for its advanced packaging is growing around 80 percent a year and expects the strength to hold through 2029 — the packaging floor, not the wafer fab, is now where AI accelerators wait in line. A single CoWoS package drawing four kilowatts is not a chip anymore; it is a heating element with a processor attached. Air cooling died somewhere below that line. Liquid cooling at the board level is dying next. What remains is putting the radiator inside the package: microchannels machined centimeters from the transistors, coolant flowing where the heat is born.

600 W to 4,100 W in five years — the package becomes the heat problem, and the heat solution moves inside it.

Cooling Is the New Architecture

The reframing here is that thermal design is climbing the stack. For thirty years, packaging was a passive discipline — connect the dies, route the power, spread the heat, done. CoWoS made packaging architectural: stack logic on HBM, tune the interconnect, and the package determines what the system can do. Now it becomes thermodynamic architecture too. The constraint on how much compute fits in a rack is set at the packaging layer, which means the cooling roadmap is a product roadmap. TSMC is effectively announcing that the company who owns the plumbing owns the scaling curve.

The validation side got its own news: a Mini-Loop line for CoWoS process steps at the Baipu site in Kaohsiung, built to compress validation cycles that currently stretch from months to under a year. That sounds like a footnote until you remember that every new packaging step — every new cooling integration, every HBM generation — needs physical validation before it ships in volume. The loop is the throttle on how fast the thermal roadmap can actually move.

For the data centers buying the output, the trajectory is unmistakable: package power in the kilowatts-per-socket range arrives soon, and the facility-side consequences — direct-to-chip loops, warm-water designs, heat reuse economics — stop being pilot projects and become procurement requirements. The industry spent two years arguing about how many chips it could manufacture. The next five will be spent on where the heat goes. TSMC has told you its answer: into the silicon, down the microchannels, out the back, and bill for the water.